COA Exam III Vocab

Question Answer
combinational element an operational element such as an AND gate or an ALU
state element a memory element, such as a register or a memory
clocking methodology the approach used to determine when data are valid and stable relative to the clock
edge-triggered clocking a clocking scheme in which all state changes occur on a clock edge
control signal a signal used for multiplexor selection or for direction the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit
asserted the signal is logically high or true
deasserted the signal is logically low or false
datapath element a unit used to operate on or hold data within a processor. In the LEGv8 implementation, the datapath elements include the instruction and data memories, the register file, the ALU, and adders
program counter (PC) the register containing the address of the instruction in the program being executed
register file a state element that consists of a set of registers that can be read and written by supplying a register number to be accessed
sign-extend to increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item
branch target address the address specified in a branch, which becomes the new program counter (PC) if the branch is taken. In the LEGv8 architecture, the branch target is given by te sum of the offset field of the instruction and the address of the branch
branch taken a branch where the branch condition is satisfied and the program counter (PC) the branch target. All unconditional branches are taken branches
branch not take (untaken branch) a branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch
truth table from logic, a representation of a logical operation by listing all the values of inputs and then in each case showing what the resulting outputs should be
don't-care term an element of a logical function in which the output does not depend on the values of all the inputs. Don't care terms may be specified in different ways
opcode the field that denotes the operation and format of an instruction
single-cycle implementation (single clock cycle implementation) an implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical
pipelining an implementation technique in which multiple instructions are overlapped in execution, much like an assembly line
structural hazard when a planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute
data hazard (pipeline data hazard) when a planned instruction cannot execute in the proper clock cycle because data that are needed to execute the instruction are not yet available
forwarding (bypassing) a method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory
load-use data hazard a specific form of data hazard in which the data being loaded by a load instruction have not yet become available when they are needed by another instruction
pipeline stall (bubble) a stall initiated in order to resolve a hazard
control hazard (branch hazard) when a proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected
branch prediction a method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome
latency (pipeline) the number of stages in a pipeline or the number of stages between two instructions during execution
nop an instruction that does no operation to change state
flush to discard instruction in a pipeline, usually due to an unexpected event
dynamic branch prediction prediction of branches at runtime using runtime information
branch prediction buffer (branch history table) a small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently take or not
branch target buffer a structure that caches the destination PC or destination instruction for a branch. It is usually organized as a cache with tags, making it more costly tha a simple preditiction buffer
correlating predictor a branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches
tournament branch predictor a branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch
exception (interrupt) an unscheduled event that disrupts program execution; used to detect overflow
interrupt an exception that comes from outside the processor (some architectures use the temr interrupt for all exceptions)
vectored interrupt an interrupt for which the address to which control is transferred is determined by the cause of the exception
imprecise interrupt (imprecise exception) interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception
precise interrupt (precise exception) an interrupt or exception that is always associated with the corrupt instruction in pipelined computers
instruction-level parallelism the parallelism among instructions
multiple issue a scheme whereby multiple instructions are launched in one clock cycle
static multiple issue an approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution
dynamic multiple issue an approach to implementing a multiple-issue processor where many decisions are made during execution by the procesor
issue slots the positions from which instructions could issue in a given clock cycle; by analogy, these correspond to positions at the starting blocks for a sprint
speculation an approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions
issue packet the set of instructions that issues together in one clock cycle; the packet may be determined statically by the compiler or dynamically by the procesor
very long instruction word (VLIW) a style instruction set architecture that launches many operations that are defined to be independent in a single-wide instruction, typicaly with many separate opcode fields
use latency number of clock cycles between a load instruction an an instruction that can use the result of the load without stalling the pipeline
register renaming the renaming of registers by the compiler or hardware to remove antidependences
antidependence (name dependence) an ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions
superscalar an advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution
dynamic pipeline scheduling hardware support for reordering the order of instruction to avoid stalls
commit unit the unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory
reservation station a buffer within a functional unit that holds the operands and the operation
reorder buffer the buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a regsiter
out-of-order execution a situation in pipeline execution when an instruction blocked from executing does not cause the following instructions to wait
in-order commit a commit in which the results of pipelined execution are written to the programmer visible state in the same order that instructions are fetched
microarchitecture the organization of the processor, including the major functional units, their interconnection, and control
architectural registers the instruction set of visible registers of a processor; for example, in LEGv8, these are the 32 integer and 32 floating-point registers
instruction latency the inherent execution time for an instruciton

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